How to debug PAC5532EVK1 with J-Link
I have debuged PAC5532EVK1 with J-Link sucessfully but first firmware I configured PF0 Pins to PWM and then I can’t debug PAC5532EVK1 with J-Link anymore. Can you tell me. How to fix it please??
Thanks you so much.
Hi Duong Hung,
Unfortunately, there is a good chance the device will not be able to be recovered. Ideally, when developing code, you would insert a delay inside of the Reset Vector Subroutine, so that in the event you have changed the configuration of the SWD ports, you have a little time to power up the system, press Erase within your IDE, and then recover the device. If there is no delay this technique will be nearly impossible as the code will most likely reconfigure the GPIO ports fractions of a second after it exits the reset subroutine. There are only two venues I can think of. You can try to, by pure chance, manage to push an Erase cycle as you power up your system. To be honest, the chances of this succeeding are extremely low, but there is always a slight chance it will work. The technique which will definitely work will be to replace the device with a fresh PAC5532 unit.
On your subsequent evaluation cycles, you may want to add the aforementioned delay, in order to ensure you can rescue the device in the event a code bug of this sort is introduced. Also, there are other tricks you can use to ensure the device is rescue-able. For example, you can program a GPIO as an input and such that when it is asserted, the SWD ports are reconfigured with their SWD functionality. You could also perform this task with an UART command. Or you could install a boot loader so you can erase the code through the UART port. Or any other technique of this sort which allows the SWD to be reinstated.
Hope the info helps!
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