It may seem a little counterintuitive to talk about PWM control for motors and not talk about the H Bridge. So before I confuse you any further, please allow me to confuse you with something else.
The H Bridge is something which has been discussed plenty out there. So I will not detail every possible angle about it, although for the subsequent code to make sense, I do need to detail my own nomenclature. In doing so, we will see most of what an H Bridge is and can do.
There is no better way to start talking about the H Bridge than by showing you the actual thing:
It is called an H Bridge because it looks like the letter “H”. And it is a Bridge because it connects two sides so that current can flow in one of two possible directions. This is the perfect topology for powering up our brushed DC motor.
On a deeper level, we can see it is composed of 4 n Channel FETs. The two left side FETs make what we will call half H Bridge U, and the two right side FETs we will call half H Bridge V. Notice they could have been called half H Bridges A or B (or L and R), but since I am parting from a 3 phase motor inverter board (whose pin names are often called U,V,W) and I will use the U and V outputs, I will go with the U and V nomenclature.
If we have sides, we also have levels. The high side FETs are called high side FETs and the low side FETs are called low side FETs. REALLY??? Who would have guessed?
We can then give these FETs proper names such as UH (U Side, High Side), UL, VH and VL. Just so that we can keep track of them, because here is where we will start confusing things… NAH! This will be a breeze for you!
The importance about an H Bridge is that it gives us the ability to control both motor shaft direction of rotation (by selecting which FETs are ON and OFF) and motor speed (by applying an ON/OFF rate to the FETs).
For example, we can control direction of current flow, which in turns specifies motor rotor direction of rotation, by enabling UH and VL or by enabling VH and UL as shown below:
The two conditions above are considered legal conditions. Do note there are two other combinations we must avoid at all costs! They are better known as shoot through and consist of enabling both UH and UL FETs, or both VH and VL FETs, at the same time. The reason is that doing so entails a very low resistance path, which will most likely increase current to disproportionate levels, not to mention cook the power switches. Hopefully my depiction below has big enough prohibition crosses…
Needless to say, trying to enable both same side FETs in code is not a good idea. There are still cases, however, when both same side FETs could end up being turned ON at the same time. This mostly happens during switchover and can be easily remedied if a “Break Before Make” (BBM) connection topology is employed.
On conventional controllers, this BBM mechanism has to be implemented in code. On the other hand, our PAC5220 has internal circuitry, referred to as Dead Time Generators, which eliminate the need to code this! This block imposes a programmable dead band period of time which ensures enough time has passed between one FET turning OFF and the other one turning ON.
If you have taken the time to read the previous INITIALIZATION post you will see two lines of code which initialize said block:
// Configuring Death Time Generators (DTG)
pac5xxx_dtg_config(DTGA0, MOTOR_LED_TICKS, MOTOR_TED_TICKS, 0, 0, 0, 0);
pac5xxx_dtg_config(DTGA1, MOTOR_LED_TICKS, MOTOR_TED_TICKS, 0, 0, 0, 0);
I will talk more about Dead Time Generators, and how to program them, on a different post.
Now, I told you previously we can control both direction and motor speed by specifying which FETs are ON and OFF. So far we have seen that selecting alternate FETs grant us the ability to control current flow direction, so how do we control speed then?
If you will recall from the INTRODUCTION post, to control motor speed what we need to do is specify how long the FETs are ON and OFF. The rate of ON and OFF we called the duty cycle. So all we have to do is choose one of the two possible legal conditions for current flow (the two that are not shoot through!) and turn their FETs ON and OFF with a controlled rate.
Not so fast! Turning FETs ON and OFF may seem as simple as turning FETs ON and OFF, but the laws of physics will be quick to get us at our own game if we are not cautious. The most nefarious aspect we have to keep in mind here, is that we are driving an inductive load and by the laws of physics, an inductive load will not allow abrupt changes in current.
What this means is that when we enable the FETs, the current will increase to some value. It should then be obvious that when we disable the FETs, the current will not be zero. Whatever it’s value is, if we try to change it abruptly, it won’t! Instead, the voltage will increase to some unwanted value. This is when stuff (as in FETs!) may break, so needless to say, we truly do not want this to happen. What can we do?
We need to let the current continue to flow such that the law is preserved. We are going to kill a couple of birds with a single stone here (not that I have anything against birds…). Basically, the way in which we are going to apply our motor control PWM will allow for our FETs to be energized while maintaining current flow.
To do so, I will always have one low side FET turned ON and apply the PWM signal on the opposing side. It will look something like this:
On this direction polarity, my VL FET will always be ON and the VH FET will be high impedance (OFF). The U Side will have the PWM which means that during TIME ON the high side FET UH will be energized (ON) and the low side will be OFF. Once the duty cycle elapses, and we move to the TIME OFF region of the PWM cycle, the UH FET is switched OFF and the UL FET will is switched ON.
Notice this switchover allows for the current to continue flowing from side U to side V as it was doing before. Of course current will be charging across the inductance during TIME ON and discharging during TIME OFF, but no abrupt change will take place, hence preserving the law.
The mechanism which allows for current to continue flowing across an inductive load in a safely manner is better known as Current Decay or Current Regulation. In this particular case we will use what is known as Slow Current Decay, because the current decays at a slow rate through both low side FETs. The topic of current regulation topologies is material for a different post.
With this PWM structure we have not only allowed current to decay safely we have in fact added a speed control mechanism as well. Motor speed will be directly proportional to the applied duty cycle, so all that we need to do is update this parameter and VOILA! Motor speed control at your disposition!
Do note that all this talk about turning this FET ON and turning this FET OFF may give you the impression there is a lot of code we need to take care of. In the following post you will see how little code we need. If you remember from previous posts, using PWM’s requires very little code because the hardware takes care of most of the required actuation.
There are only two things we need to do in code, and this only happens sporadically:
1. To configure each GPIO resource as a GPIO or a PWM output.
2. To enable the FET which happens to be configured as a GPIO on its respective Output Register.
In order to understand this better, we need to take a look at some registers. As it turns out, each H Bridge FET is connected to a PORT A resource. All of this stuff is detailed on the PAC5220 Users Guide’s chapter 25, so feel free to refer to it for further information. For the time being, please accept this mapping:
PA0 maps to DRL0 (low Side 1 which we will use as UL)
PA1 maps to DRL1 (low side 2 which we will use as VL)
PA2 maps to DRL2 (low side 3 which is WL and we will not use on this project)
PA3 maps to DRH3 (high side 1 which we will use as UH)
PA4 maps to DRH4 (high side 2 which we will use as VH)
PA5 maps to DRH5 (high side 3 which is WH and we will not use on this project)
The first step above (to configure each PAx pin as a GPIO or PWM output) is taken care of by writing to the PAPSEL register.
Notice each two bits take care of one PAx resource. All of them become GPIO resources if we write a 00b to their respective location. The other combinations are specified below. For example, when we want PA3 to behave like a PWM, we can either do 01b, 10b or 11b. I have underlined which resources we are supposed to use. In the case of PA3 we want to use PWMA4, so we will use the combination 10b.
As explained earlier, we have two legal combinations:
1. U side is PWM and V side is LO
2. V side is PWM and U side is LO
When a side is meant to be a PWM we will configure it with the PWM variant (e.g. 01b or 10b depending on the resource), and when a side is meant to be LO, we will configure it as a GPIO (e.g. 00b).
Simply configuring a resource as a GPIO, however, does not enable the FET. When we enable the resource as a GPIO we are simply stating that PAx pin will be an input or an output. We still need to configure the resource as an output and ensure the output is set to HI (which turns the low side FET ON).
To enable low side FETs we will need to look at the PAOUT register.
I will show you on the next posting the code where we modify PAOUT in order to enable and disable the low side FETs. All you need to understand at this time is that we will either make PA0 HI (UL FET is turned ON) or PA1 HI (VL FET is turned ON).
And so a question must arise: But where did we configure PA0 and PA1 as outputs? We actually did this during our initialization post on this line of code:
We will not need to change whether PA0 and PA1 are inputs or outputs on a continuous basis, so we can do this once during the init. We will, on the other hand, need to change continuously whether the low side FET will need to be enabled/disabled. But as you will see later on, this is actually quite easy and takes very little code.
Hopefully this is not too messy and you have managed to follow the discussion. Next step will be to take a look at the code which actually configures the H Bridge for direction and modifies the PWM’s duty cycles.